course outline -aiou--Digital logic -code No 3409-Autumn 2014

  Solved course

  Solved course outline -aiou--Digital logic -code No  3409-Autumn 2014

AIOU

 

 

 

 

 

 

Unit #1

Binary  System,

Binary Numbers Based Conversion of Octal, Hexadecimal and Binary,

Complements, Binary Codes, Binary Logic and ICs

 Follow these links
Binary Numbers Based Conversion of Octaloctal number system
hexadecimal and binary
Complements
Binary Codes 
Binary Logic and ICs

Unit # 2

 Boolean Algebra and Logic Gates

Definitions, Theorems and Properties, Boolean Functions, Canonical and

STD Forms, other Logical Properties, Gates
Follow these links
Defination of bolean algebra and logic gates
Theorem and properties
 Boolean Functions
 Canonical and STD forms
other Logical Properties and gates


Unit # 3

Simplification of Boolean Function

Map Method, NAND and NOR Implementation, Tabulation Method,

Prime Implement
Follow these links
map method
NAND and NOR Implementation
  Tabulation Method
Tabulation method
prime impliment

Unit # 4:

Combination Logic

Design Procedure, Adder, Subtractors, Code Conversation Analysis

Procedure, NAND and

NOR Functions, Ex OR and Ex NOR Function
 Follow these links
 Design Procedure,
 Adder, Subtractors,
 Code Conversation Analysis Procedure, 
NAND and NOR Functions,
 Ex OR and Ex NOR Function

Unit #5

:Combination Logic with MSI and LSI

Binary Parallel Adder, Decimal Adder, BCD Counter, Magnitude

Compactor, Decoders, Demultiplexers, Encoder, Multiplexer, ROM, PLA

 Follow these links
 Binary Parallel Ad, 
BCD Counter, 
MagnitudeCompactor, 
Decoders, Encoder, Multiplexer,
Demultiplexers, 
ROM, PLA

Unit # 6

Sequential Logic

Introduction,

Flip Flop, Triggering, State Reduction Excitation Table,

Design Procedure, Design of Counter

 Follow these links

Introduction,

Flip Flop, 
Triggering, 
State Reduction Excitation Table,

Design Procedure, 
Design of Counter

Unit #7

:

Register, Counter, and Memory Unit

Register Counter, Timing Sequence, Memory Unit

 Follow these links
Register Counter, 
Timing Sequence, 
Memory Unit 

Unit #8

Asynchronous Sequential Logic

Analysis Procedure, Circuits

with Latches, Design Procedure, Reductions

of State and Flow Tables, Race Free State Assignment
 Follow these links
 Analysis Procedure,
 Circuits with Latches, 
Design Procedure, 
Reductions of State and Flow Tables, 
Race Free State Assignment-
example 

Unit #9

:

Digital Integrated Circuits

Bipolar Transistor Characteristics, RTL and DTL Circuits, Transistor,

Transistor Logic, Emitter Coupled Logic (ECL), Metal

Oxide Semiconductor (MOS), CMOS

Follow these links

Bipolar Transistor Characteristics
, RTL and DTL Circuits,
 Transistor,

Transistor Logic,
 Emitter Coupled Logic (ECL), 
 Metal Oxide Semiconductor (MOS),
 CMOS